The present invention relates generally to a semiconductor memory device, and more particularly to a static random access memory device having a high packing density, a super-low power dissipation and a high soft-error immunity, as well as a method of manufacturing the same.
As can be seen in an equivalent circuit diagram shown in FIG. 3, the static random access memory cell of a high packing density known heretofore in which there are employed insulated gate field-effect transistors (IGFET in abbreviation and also referred to as the MOS transistor in the most general term) is composed of a flip-flop circuit constituted by a pair of driver MOS transistors T.sub.1 and T.sub.2 cross-coupled to each other, highly resistive loads R.sub.1 and R.sub.2 connected to a pair of storage nodes N.sub.1 and N.sub.2 of the flip-flop circuits for supplying extremely small currents to the storage nodes N.sub.1 and N.sub.2 for retaining data thereat, respectively, and transfer MOS transistors T.sub.3 and T.sub.4 connected to the storage nodes N.sub.1 and N.sub.2 for performing "write" and "read" of the data retained thereat, wherein the flip-flop circuit is supplied with a power supply voltage V.sub.cc and the ground potential with data lines 1 and 1' being connected to the transfer MOS transistors and with a common gate constituting a word line. For operation of such static random access memory cell, the word line is activated for allowing the data of "High" or "Low" to be stored at the storage nodes N.sub.1 and N.sub.2, or, alternatively, to allow the states of the storage nodes to be read out through the data line and the transfer MOS transistors, as is well known in the art.
FIG. 4 shows in a plan view a typical one of the static random access memory cells of the prior art described above, which is disclosed in, for example, "NIKKEI ELECTRONICS", May 21, 1984, pp. 181-199 and Dec. 30, 1985, pp. 117-145. The prior art static random access memory cell will be described below in more detail by reference to FIG. 4.
In FIG. 4, reference symbols 57c and 57d denote gate electrodes of the driver MOS transistors T.sub.1 and T.sub.2, respectively, and 5a denotes a common gate electrode of transfer MOS transistors T.sub.3 and T.sub.4. A highly concentrated n-type impurity region 3d which is to constitute a drain of the driver MOS transistor T.sub.1 is provided in common to an n-type impurity region of the transfer MOS transistor 3d. Further, a highly concentrated n-type impurity region 3e which is to serve as a drain of the driver MOS transistor T.sub.2 is electrically connected to an n-type impurity region 3c of the transfer MOS transistor T.sub.4 by way of the gate electrode 5b while the gate electrode 5c of the driver MOS transistor T.sub.2 is electrically connected to the n-type impurity region 3d which is common to both the transfer MOS transistor T.sub.3 and the driver MOS transistor T.sub.1 to thereby realize the cross-coupling of the flip-flop circuit of the static random access memory cell.
Holes 6a and 6b for interconnection are formed in the gate electrodes 5b and 5c, wherein highly resistive polysilicon films 7c and 7d are connected to the gate electrodes 5b and 5c through low resistive polysilicon films 7a and 7b, respectively. Further, a low resistive polysilicon film 7e constitutes a common power supply voltage line connected to the highly resistive polysilicon film 7e.
Aluminum (Al) electrodes 9a and 9b which are to serve as two data lines in the memory cell are electrically connected to highly concentrated impurity regions 3a and 3b of the transfer MOS transistors T.sub.4 and T.sub.3 through holes 8a and 8b for interconnection, respectively.